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ultra - compact, high - performance, high - frequency drmos device ZSPM9015 datasheet ? 2016 integrated device technology, inc. 1 january 25, 2016 brief description the ZSPM9015 is idt ?s next - generation, fully optimized, ultra - compact, integrated mosfet plus driver power stage solution for high - current, high - frequency, synchronous buck dc - dc applications. the ZSPM9015 integrates a driver ic, two power mosfets, and a bootstrap schottky d iode into a thermally enhanced, ultra - compact 6x6mm package. with an integrated approach, the complete switching power stage is optimized with regard to driver and mosfet dynamic performance, system inductance, and power mosfet r ds(on) . the ZSPM9015 uses i nnovative high - performance mosfet technology, which dramatically reduces switch ringing, eliminat - ing the need for a snubber circuit in most buck converter applications. a driver ic with reduced dead times and propagation delays further enhances the perfor mance. a thermal warning function indicates if a potential over - temper - ature situation (>150 c) has occurred. an automatic thermal shutdown activates if an over - temperature condition (>180 c) is detected. the ZSPM9015 also incorporates a zero current detec tion mode (zcd) for improved light - load efficiency and provides a tri - state 3.3v and 5v pwm input for compatibility with a wide range of pwm controllers. the ZSPM9015 drmos is compatible with idt ?s zspm1000, a leading - edge configurable digital power - ma nagement system controller designed for non- isolated point - of - load (pol) supplies. features ? high - current handling: up to 35 a ? pwm input capable of 3.3v and 5v ? optimized for switching frequencies up to 1mhz ? zero - c urrent d etection and under - voltage lockout (uvlo) ? thermal shutdown and w arning flag for over - temperature conditions ? driver output disable function (disb# pin) ? integrated schottky diode technology in the low - side mosfet ? integrated bootstrap schottky diode ? adaptive gate dri ve timing for shoot - through protection be n efits ? improved efficiency with zero current detection ? clean switching waveforms with minimal ringing ? based on the intel? 4.0 drmos standard ? 72% space - saving compared to conventional discrete solutions ? high current handling ? optimized for use with idt ?s zspm1000 true digital pwm controller available support ? zspm8015 - kit: evaluation kit for ZSPM9015 physical characteristics ? operation temperature: 0c to +150c ? v in : 4.5v to 25v (typical 12v) ? i out : up to 35 a ? lo w - profile smd package: 6mmx6mm qfn40 ? idt green packaging and rohs compliant typical application
ultra - compact, high - performance, high - frequency drmos device ZSPM9015 datasheet ? 2016 integrated device technology, inc. 2 january 25, 2016 typical applications ? high - performance gaming motherboards ? compact blade servers, v c ore and non - v c ore dc- dc converters ? desktop computers, v c ore and non - v c ore dc- dc converters ? workstations ? high - c urrent dc - dc p oint - of - l oad c onverters ? networking and t elecom m icroprocessor v oltage r egulators ? small f orm - f actor v oltage r egulator m odules v cin gh d boot gl thermal warning gl logic pwm thwn# pgnd phase vin boot (q1) hs power mosfet (q2) ls power mosfet gh logic level shift anti-cross conduction vswh gl gh logic vcin disb# zcd_en# thermal shutdown uvlo cgnd ZSPM9015 ZSPM9015 block diagram ordering information product sales code description package ZSPM9015 zi 1r ZSPM9015 rohs - compliant qfn40 ? junction t emperature range: 0c to 150c reel zspm8015 - kit evaluation kit for ZSPM9015 kit corporate headquarters 6024 silver creek valley road san jose, ca 95138 www.idt.com sales 1- 800- 345- 7015 or 408 - 284- 8200 fax: 408 - 284- 2775 www.idt.com/go/sales tech support www.idt.com/go/support disclaimer integrated device technology, inc. (idt) reserves the right to modify the products and/or specifications described herein at any time, without notice, at idt's sole discretion. performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer pro ducts. the information contained herein is provided without representation or warranty of any kind, whether express or implied, in cluding, but not limited to, the suitability of idt's products for any particular purpose, an implied warranty of merchantability, or non - infringement of the intellectual property rights of others. this document is presented only as a guide and does not co nvey any license under intellectual property rights of idt or any third parties. idt's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunct ion of an idt product can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own risk, absent an express, written agreement by idt. integrat ed device technology, idt and the idt logo are trademarks or registered trademarks of idt and its subsidiaries in the united states and other countries. other trademarks used herein are the property of idt or their respective third party owners. for datash eet type definitions and a glossary of common terms, visit www.idt.com/go/glossary . all contents of this document are copyright of integrated device technology, inc. all rights reserved.
ZSPM9015 datasheet ? 2016 integrated device technology, inc. 3 january 25, 2016 contents 1 ic characteristics ............................................................................................................................................. 5 1.1. absolute maximum ratings ....................................................................................................................... 5 1.2. recommended operating conditions ....................................................................................................... 6 1.3. electrical parameters ................................................................................................................................ 6 1.4. typical performance characteristics ......................................................................................................... 8 2 functional description .................................................................................................................................... 10 2. 1. vcin and disable (disb#) ...................................................................................................................... 10 2.2. thermal warning flag (thwn#) and thermal shutdown ...................................................................... 11 2.3. tri - state pwm input ................................................................................................................................. 12 2.4. adaptive gate drive circuit ..................................................................................................................... 12 2.5. zero current detection mode (zcd_en#) .............................................................................................. 13 3 application design .......................................................................................................................................... 15 3.1. sup ply capacitor selection ..................................................................................................................... 15 3.2. bootstrap circuit ...................................................................................................................................... 15 3.3. power loss and efficiency testing procedures ...................................................................................... 16 4 pin configuration and package ...................................................................................................................... 17 4.1. available packages ................................................................................................................................. 17 4.2. pin description ......................................................................................................................................... 18 4.3. pac kage dimensions ............................................................................................................................... 19 5 circuit board layout considerations .............................................................................................................. 20 6 glossary ......................................................................................................................................................... 21 7 ordering informa tion ...................................................................................................................................... 22 8 related documents ........................................................................................................................................ 22 9 document revision history ............................................................................................................................ 22 list of figures figure 1.1 power loss vs. output current ........................................................................................................... 8 figure 1.2 efficiency vs. outp ut current .............................................................................................................. 8 figure 1.3 power loss vs. output current ........................................................................................................... 8 figure 1.4 efficiency vs. output current .............................................................................................................. 8 figure 1.5 power loss vs. switching frequency ................................................................................................. 9 figure 1.6 power loss vs. input voltage ............................................................................................................. 9 figure 1.7 power loss vs. control input voltage ................................................................................................ 9 figure 1.8 power loss vs. output voltage .......................................................................................................... 9 figure 1.9 control input current vs. switching frequency ................................................................................. 9 figure 1.10 control input current vs. control input voltage ................................................................................. 9 figure 2.1 block diagram and typical application circuit with pwm control ................................................... 10
ZSPM9015 datasheet ? 2016 integrated device technology, inc. 4 january 25, 2016 figure 2.2 thermal warning flag (thwn#) operation ..................................................................................... 11 figure 2.3 pwm and tri - state timing diagram ................................................................................................. 12 figure 2.4 zcd_en# timing diagram ............................................................................................................... 14 figure 3.1 power loss measurement block diagram ....................................................................................... 15 figure 4.1 pin - out pqfn40 package ................................................................................................................ 17 figure 4.2 qfn40 physical dimensions and recommended footprint ............................................................ 19 figure 5.1 pcb layout example ........................................................................................................................ 21 list of tables table 2.1 uvlo and disable logic .................................................................................................................. 11 table 2.2 zcd mode operation (zcd_en# = low) and switch states ......................................................... 13
ZSPM9015 datasheet ? 2016 integrated device technology, inc. 5 january 25, 2016 1 ic characteristics 1.1. absolute maximum ratings the absolute maximum ratings are stress ratings only. the device might not function or be operable above the recommended operating conditions. stresses exceeding the absolute maximum ratings might also damag e the device. in addition, extended exposure to stresses above the recommended operating conditions might affect device reliability. idt does not recommend designing to the ?absolute maximum ratings.? parameter symbol conditions min max units maximum voltage ? vcin pin - 0.3 7.0 v maximum voltage ? pwm, disb#, thwn# and zcd_en# pins - 0.3 6.5 v maximum voltage ? vin and vshw pin s - 0.3 30 v maximum voltage to boot pin ? vswh pin - 0.3 7.0 v maximum voltage to boot pin ? pgnd pin 35.0 v maximum voltage to boot pin ? pgnd pin < 50ns 40.0 v maximum sink current ? thwn# pin i thwn# 30 ma maximum output current i out 35 a thermal resistance, high - side mos fet jpcb 13 c/w thermal resistance, low - side mos fet jpcb 5 c/w operating junction temperature t j 0 +150 c storage temperature range t stor -55 +150 c electrostatic discharge protection esd jedec jesd22 - a114 hbm class 1b latch - up protection lu jedec jesd78 class 1 level a moisture sensitivity level msl 3
ZSPM9015 datasheet ? 2016 integrated device technology, inc. 6 january 25, 2016 1.2. recommended operating conditions the ?recommended operating conditions? table defines the conditions for actual device operation. recom - mended operating conditions are specified to ensure optimal performance to the datasheet specifications. idt does not recommend exceeding them or designing to the ?absolute maximum ratings.? parameter symbol conditions min typ max units control input voltage v cin 4.5 5.0 5.5 v input supply voltage 1) v in 4.5 12.0 25 v 1) operating at high v in can create excessive ac overshoots on the vswh - to - gnd and boot - to - gnd nodes during mosfet switching transients. for reliable drmos operation, vswh - to - gnd and boot - to - gnd must remain at or below the "absolute maximum ratings" shown in the table above. refer to sections 3 and 5 of this datasheet for additional information. 1.3. electrical parameters note: performance is guarantee d ove r th e indicate d operatin g temperatur e rang e b y desig n and/o r charac teri - zatio n teste d a t t j = t a = 25 c . low duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible . typical values are v in = 12v, v cin = 5v, ambient temperature t amb = - 10oc to + 100 c unless otherwise noted. parameter symbol conditions min typ max units supply current vcin current (n ormal m ode) disb# = 5v, pwm = osc, fsw = 400khz 14 2 0 ma vcin current ( disabled m ode) disb# = gnd 15 30 a under - voltage lock - out uvlo threshold uvlo v cin rising 3.8 4.35 4.5 v uvlo hysteresis uvlo _hyst 0.150 0. 2 0.250 v pwm input p wm input resistance 63 k pwm input bias voltage 1.7 v pwm high - level voltage v ih _pwm 2.65 v pwm tri -s tate level voltage v tri _ pwm 1.4 2.0 v pwm low - level voltage v il _pwm 0.7 v tri - state shut off time t d_h old - off 250 ns
ZSPM9015 datasheet ? 2016 integrated device technology, inc. 7 january 25, 2016 disb# input high - level input voltage v ih_disb# 2 .0 v low - level input voltage v il_disb# 0.8 v hysteresis 500 mv propagation delay t pd_disb 20 40 ns zero c urrent detect ion high - level input voltage v ih_zcd_en# 2 .0 v low - level input voltage v il_zcd_en# 0.8 v zcd threshold -6 mv zcd timer t zcd_disb 250 ns thermal warning flag activation temperature t act 150 c reset temperature t rst 135 c thermal shutdown activation temperature 180 oc reset temperature t rst _sd 135 c boot diode forward - voltage drop v f vcin = 5v, forward bias current = 2ma 0.1 0.4 0.6 v
ZSPM9015 datasheet ? 2016 integrated device technology, inc. 8 january 25, 2016 1.4. typical performance characteristics test conditions: v in =12v, v out =1.0v, v cin =5v, l out =250nh, t amb =25c, and natural convection cooling, unless otherwise specified. figure 1 . 1 power loss vs. output current figure 1 . 2 efficiency vs. output current figure 1 . 3 power loss vs. output current figure 1 . 4 efficiency vs. output current 0 1 2 3 4 5 6 7 8 9 0 5 10 15 20 25 30 35 40 module power loss, p mod (w) module output current, i out (a) khz khz khz khz v in v, v cin v, v out v module efficiency, (%) module output current, i out (a) khz khz khz khz v in v, v cin v, v out v module power loss, p loss (w) module output current, i out (a) c enaled c disaled v in v, v cin v, v out v, f sw khz % % % % % % % % % % % module efficiency, (%) module output current, i out (a) c enaled c disaled v in v, v cin v, v out v, f sw khz
ZSPM9015 datasheet ? 2016 integrated device technology, inc. 9 january 25, 2016 figure 1 . 5 power loss vs. switching frequency figure 1 . 6 power loss vs. input voltage figure 1 . 7 power loss vs. control input voltage figure 1 . 8 power loss vs. output voltage figure 1 . 9 control input current vs. switching frequency figure 1 . 10 control input current vs. control input voltage 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 100 200 300 400 500 600 700 800 900 1000 1100 nralized dule er ss dule sicin freuenc, f sw khz v in = 12v, v cin = 5v, v out = 1v, i out = 30a 0.95 1.00 1.05 1.10 1.15 1.20 1.25 1.30 5 10 15 20 25 nralized dule er ss dule inu vlae, v in v v cin = 5v, v out = 1v, f sw = 300khz, i out = 30a 0.96 0.97 0.98 0.99 1 1.01 1.02 1.03 1.04 1.05 4.50 4.75 5.00 5.25 5.50 nralized dule er ss cnrl inu vlae, v cin v v in = 12v, v out = 1v, f sw = 300khz, i out = 30a 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 nralized dule er ss dule ouu vlae, v out v v in = 12v, v cin = 5v, f sw = 300khz, i out = 30a 0 5 10 15 20 25 30 35 40 45 100 200 300 400 500 600 700 800 900 1000 1100 cnrl inu curren, i cin a dule sicin freuenc, f sw khz v in = 12v, v cin = 5v, v out = 1v, i out = 0a 9.0 9.5 10.0 10.5 11.0 11.5 12.0 12.5 13.0 4.50 4.75 5.00 5.25 5.50 cnrl inu curren, i cin a cnrl inu vlae, v cin v v in = 12v, v out = 1v, f sw = 300khz, i out = 0a
ZSPM9015 datasheet ? 2016 integrated device technology, inc. 10 january 25, 2016 2 functional description the ZSPM9015 is a driver - plus - mos fet module optimized for the synchronous buck converter topology. a single pwm input signal is all that is required to properly drive the high - side and the low - side mosfets. it is capable of driving speeds up to 1mhz. figure 2 . 1 block diagram and typical application circuit with pwm control c vin pwm control v 5v = 4.5v to 5.5v v in = 4.5v to 25 v open drain output v out c boot enabled disabled on off l out c out r boot c vcin v cin gh d boot gl thermal warning gl logic pwm thwn# pgnd phase vin boot (q1) hs power mosfet (q2) ls power mosfet gh logic level shift anti-cross conduction vswh gl gh logic vcin disb# zcd_en# thermal shutdown uvlo cgnd ZSPM9015 2.1. vcin and disable (disb#) the vcin pin is monitored by the under - voltage lockout (uvlo) circuit. when v cin rises above ~ 4.35 v, the driver is enabled. when v cin falls below ~4.1 v, the driver is disabled (gh, gl= 0; see table 2 . 1 and section 4.2 ). the driver can also be disabled by pulling the disb# pin low (disb# < v il_disb # ; see section 1.3 ) , which holds both gl and gh low regardless of the pwm input stat e. the driver can be enabled by raising the disb# pin voltage high (disb# > v ih_disb # ). i t is advisable not to leave the disb# floating.
ZSPM9015 datasheet ? 2016 integrated device technology, inc. 11 january 25, 2016 table 2 . 1 uvlo and disable logic uvlo circuit disb# driver state on x disabled (g h=0 , gl=0) off low disabled (g h=0 , gl=0) off high enabled off open disabled (g h=0 , gl=0) on = ulvo circuit is active and the driver output is disabled. the output will not respond to the pwm input under any condition. off = ulvo is non - active and the output operates normally. the output will respond to the pwm input provide d the conditions are correct; e.g. , not in t hermal s hutdown. 2.2. thermal warning flag ( thwn# ) and thermal s hutdown the ZSPM9015 provides a thermal warning flag ( thwn # ) to indicate over - temperature conditions. the thermal warning flag uses an open - drain output that pulls to cgnd when the activation temperature (150c) is reached. the thwn# output returns to the high - impedance state once the temperature falls to the res et temperature (135c). for use, the thwn# output requires a pull - up resistor, which can be connected to vcin. figure 2 . 2 thermal warning flag ( thwn# ) operation if the temperature exceed s 180oc then the part will enter thermal shutdown and turn off both mosfets. upon the temperature falling below 15 5oc, the part will resume operation. activation temperature d i t thermal warning normal operation high low reset temperature g 135 c 150 c driver temperature voltage at thwn#
ZSPM9015 datasheet ? 2016 integrated device technology, inc. 12 january 25, 2016 2.3. tri - state pwm input the ZSPM9015 incorporates a tri - state pwm input gate drive design. the tri - state gate drive has both logic high and low levels, with a tri - state shutdown voltage window. when the pwm input signal enters and remains within the tri - state voltage window for a defined hold - off time (t d_hold -off ), both gl and gh are pulled low. this feature enables the gate drive to shut down both the high and low side mosfets using only one co ntrol signal. for example, this can be used for phase shedding in multi - phase voltage regulators. when exiting a valid tri - state condition, the ZSPM9015 follows the pwm input command. if the pwm input goes from tri - state to low, the low - side mosfet is turn ed on. if the pwm input goes from tri - state to high, the high - side mosfet is turned on, as illustrated in figure 2 . 3 . the ZSPM9015 ?s design allows for short propagation delays when exiting the tri - state window . figure 2 . 3 pwm and tri -s tate timing diagram t 0 v vdd tri - s tate pwm gh 0 v t t 0 v gl t d _ holdoff t d _ holdoff 2.4. adaptive gate drive circuit the low - side driver (gl) is designed to drive a ground - referenced low r ds(on) n - channel mosfet. the bias voltage for gl is internally connected between vcin and p gnd. the gl output follows the inverse of the pwm input with the exception that it is held low under any of the following conditions: a) the driver is disabled (disb#=0v) ; b) the pwm signal is held within the tri - state window for longer than the tri - state hold - off time, t d_holdoff ; or c) specific circuit conditions that occur while in zcd m ode (see section 2.5 for further details).
ZSPM9015 datasheet ? 2016 integrated device technology, inc. 13 january 25, 2016 the high - side driver (gh) is designed to drive a floating n - channel mosfet. the bias voltage for the high - side driver is developed by a bootstrap supply circuit referenced to the switch node (vswh) pin. this circuit consists of an internal schottky diode, an external bootstrap capacitor (c boot ) , and the optional r boot if used. during startup, the vswh pin is held at pgnd, allowing c boot (see section 3.2 ) to charge to v cin through the internal diode. when the pwm input goes high, gh begins to charge the gate of q1, the high - side mosfet. during this tr ansition, the charge is removed from c boot and delivered to the gate of q1. as q1 turns on, v swh rises to v in , forcing the boot pin to v in + v boot , which provides sufficient v gs enhancement for q1. to complete the switching cycle, q1 is turned off by pull ing gh to v swh . c boot is then recharged to v cin when v swh falls to pgnd. the gh output follows the pwm input except that it is held low when either a) the driver is disabled (disb#=0v) or b) the pwm signal is held within the tri - state window for longer than the tri - state hold - off time, t d_holdoff . the ZSPM9015 design ensures minimum mosfet dead time while eliminating potential shoot - through (cross - conduction) currents. it achieves this by monitoring the state of the mosfets and adjust s the gate drive adaptively to prevent simultaneous conduction. when the pwm input goes high, the gate of the low side mosfet (g l pin) will go low after a propagation delay. the time it takes for the low side mosfet to turn off is dependent on the gate cha rge on the low side mosfet gate. the ZSPM9015 monitors the gate voltage of both mosfets to determine the conduction status of the mosfets . once the low - side mosfet is turned off , an internal timer wil l delay the turn on of the high - side mosfet. similarly, when the pwm input pin goes low , the converse occurs. 2.5. zero current detection mode (zcd_en#) zero current detection (zcd) mode allows higher converter efficiency under light - load conditions. when the zc d f eature is disabled (zcd_en# is high) , the ZSPM9015 will operate in the normal pwm m ode in which the synchronous buck converter works in synchronous mode. if the zcd_en# is set low , then the zs pm9015 will operate in the zcd m ode , an d in this mode , the ZSPM9015 can prevent discharging of the output capacitors as the filter inductor current attempts reverse current flow. i f the pwm goes high , gh will go high after the non - overlap delay time . d uring this period , the zcd timer is inactive and thus reset. i f the pwm goes low , gl will go high after the non - overlap delay time and stay high for the duration of the zcd timer ( t zcd_disb ) ; see section 1.3 . during this pe riod zcd operation is disabled . once this timer has expired, vs wh will be monitored for zero current detection and gl will go low if a zero - current condition is detected. the zcd threshold (see section 1.3 ) on vswh to determine zero current undergoes an auto - calibration cycle every time disb# is brought from low to high . this auto - calibration cycle takes 25 s to complete . table 2 . 2 zcd mode operation (zcd_en# = low) and switch states pwm input zcd status gh gl high zcd t imer is r eset (inactive) high low low positive i nductor c urrent low high low zer o i nductor c urrent low low tri - state x low low
ZSPM9015 datasheet ? 2016 integrated device technology, inc. 14 january 25, 2016 figure 2 . 4 zcd_en # timing diagram see figure 2.3 for the definitions of the timing parameters. pwm 0v t 0v t 0v t zcd_en# 0v t 0a t gh gl i l t zcd_disb zcd o ccurrence
ZSPM9015 datasheet ? 2016 integrated device technology, inc. 15 january 25, 2016 3 application design 3.1. supply capacitor selection for the supply input (vcin), a local ceramic bypass capacitor (c cvin ) is required to reduce noise and is used to supply the peak transient currents during gate drive switching action. recommendation: use at a 1f to 4.7f capacitor with an x7r or x5r dielectric. keep this capacitor close to the vcin pin, and connect it t o the cgnd ground plane with vias. 3.2. bootstrap circuit the bootstrap circuit uses a charge storage capacitor (c boot ), as shown in figure 3 . 1 . a bootstrap capacitance of 100nf using a x7r or x5r capacitor is typically adequate. a series bootstrap resistor might be needed for specific applications to improve switching noise immunity . the boot resistor might be required when operating with v in above 15 v, and it is effective at controlling the high - side mosfet turn - on slew rate and v swh overshoot. typically, r boot values from 0.5 to 3.0 are effective in reducing v swh overshoot. figur e 3 . 1 p ower loss measurement block diagram vcin pwm disb # zcd _ en # pgnd phase vin boot vswh zspm 90 15 thwn # cgnd c vin pwm input v 5 v v in c v cin v out c boot l out a i 5 v open drain output disb a i in a i out v sw c out r boot on off v
ZSPM9015 datasheet ? 2016 integrated device technology, inc. 16 january 25, 2016 ( ) out sw sw i v p ? = ( ) ( ) v 5 v 5 in in in i v i v p ? + ? = ( ) out out out i v p ? = ( ) sw in module _ loss p p p ? = ( ) out in board _ loss p p p ? = % p p 100 eff in out board ? ? ? ? ? ? ? ? ? = % p p 100 eff in sw module ? ? ? ? ? ? ? ? ? = 3.3. power loss and efficiency testing procedures the circuit in figure 3 . 1 has been used to measure power losses in the following example. the efficiency has been calculated based on the equations (1) through (7) . power loss calculations in watts: (1) (2) (3) (4) (5) efficiency calculations: (6) (7)
ZSPM9015 datasheet ? 2016 integrated device technology, inc. 17 january 25, 2016 4 pin configuration and package 4.1. available packages the ZSPM9015 is av ailable in a 40 - lead clip - bond qfn package. the pin - out is shown in figure 4 . 1 . see figure 4 . 2 for the mechanical drawing of the package. figure 4 . 1 pin - out pqfn40 package
ZSPM9015 datasheet ? 2016 integrated device technology, inc. 18 january 25, 2016 4.2. pin description pin name description 1 zcd_en # enable zero current detection mode . advisable not to leave floating . 2 vcin ic bias supply. a 1 f (minimum) ceramic capacitor is recommended from this pin to cgnd. 3 nc no connection. 4 boot bootstrap supply input. provides voltage supply to the high - side mosfet driver. connect a bootstrap capacitor from this pin to phase. 5, 37 & pad 41 cgnd ic ground. ground return for ZSPM9015 . 6 gh gate high. for manufacturing test only. this pin must float: it must not be connected. 7 phase switch node pin for bootstrap capacitor routing; electrically shorted to vswh pin. 8 nc no connection. 9 - 14 & pad 42 vin input power voltage (output stage supply voltage). 15, 29 - 35 & pad 43 vswh switch node. provides return for high - side bootstrapped driver and acts as a sense point for the adaptive shoot - through protection. 16 ? 28 pgnd power ground (output stage ground). source pin of the low - side mosfet. 36 gl gate low. for manufacturing test only. this pin must float. it must not be connected. 38 thwn# thermal warning flag. when temperature exceeds the trip limit, the output is pulled low. this pin has a maximum current c apability of 30ma. 39 disb# output disable. when low, this pin disables the p ower mos fet switching (gh and gl are held low). advisable not to leave floating . 40 pwm pwm signal input. this pin accepts a tri - state 3.3 v or 5v pwm signal from the controller.
ZSPM9015 datasheet ? 2016 integrated device technology, inc. 19 january 25, 2016 4.3. package dimensions figure 4 . 2 qfn40 physical dimensions and recommended footprint
ZSPM9015 datasheet ? 2016 integrated device technology, inc. 2 0 january 25, 2016 5 circuit board layout considerations figure 5 . 1 provides an example of a proper layout for the ZSPM9015 and critical components. all of the high - current paths, such as the v in , v swh , v out , and gnd copper traces, should be short and wide fo r low inductance and resistance. this technique achieves a more stable and evenly distributed current flow, along with enhanced heat radiation and system performance. the following guidelines are recommendations for the printed circuit board (pcb) designer : 1. input ceramic bypass capacitors must be placed close to the vin and pgnd pins. this helps reduce the high - current power loop inductance and the input current ripple induced by the power mosfet switching operation. 2. the v swh copper trace serves two purpose s. in addition to being the high - frequency current path from the drmos package to the output inductor, it also serves as a heat sink for the low - side mosfet in the drmos package. the trace should be short and wide enough to present a low - impedance path for the high - frequency, high - current flow between the drmos and inductor to minimize losses and drmos temperature rise. note that the vswh node is a high - voltage and high - frequency switching node with a high noise potential. care should be taken to minimize c oupling to adjacent traces. since this copper trace also acts as a heat sink for the lower mosfet, the designer must balance using the largest area possible to improve drmos cooling with maintaining acceptable noise emission. 3. locate the output inductor clo se to the ZSPM9015 to minimize the power loss due to the vswh copper trace. care should also be taken so that the inductor dissipation does not heat the drmos. 4. the power mosfets used in the output stage are effective for minimizing ringing due to fast swit ching. in most cases, no vswh snubber is required. if a snubber is used, it should be placed close to the vswh and pgnd pins. the resistor and capacitor must be the proper size for the power dissipation. 5. vcin and boot capacitors should be placed as close as possible the vcin - to - cgnd and boot - to - phase pin pairs to ensure clean and stable power. routing width and length should be considered as well. 6. the layout should include a placeholder to insert a small - value series boot resistor (r boot ) between the boot capacitor (c boot ) and the ZSPM9015 boot pin. the boot - loop size, including r boot and c boot , should be as small as possible. the boot resistor may be required when operating with v in above 15v. the boot resistor is effective for controlling the high - side mo sfet turn - on slew rate and v swh overshoot. r boot can improve the operating noise margin in synchronous buck designs that might have noise issues due to ground bounce or high positive and negative v swh ringing. however, inserting a boot resistance lowers th e drmos efficiency. efficiency versus noise trade - offs must be considered. r boot values from 0.5 to 3.0 are typically effective in reducing v swh overshoot. 7. the vin and pgnd pins handle large current transients with frequency components greater than 100mh z. if possible, these pins should be connected directly to the vin and board gnd planes. important: the use of thermal relief traces in series with these pins is discouraged since this adds inductance to the power path. added inductance in series with the vin or pgnd pin degrades system noise immunity by increasing positive and negative v swh ringing . 8. connect the cgnd pad and pgnd pins to the gnd plane copper with multiple vias for stable grounding. poor grounding can create a noise transient offset voltage level between cgnd and pgnd. this could lead to faulty operation of the gate driver and mosfets.
ZSPM9015 datasheet ? 2016 integrated device technology, inc. 21 january 25, 2016 9. ringing at the boot pin is most effectively controlled by close placement of the boot capacitor. do not add an additional boot to pgnd capacitor; this could le ad to excess current flow through the boot diode. 10. it is advisable not to float t he zcd_en# and disb# pins. 11. use multiple vias on each copper area to interconnect top, inner, and bottom layers to help distribute current flow and heat conduction. vias should be relatively large and of reasonably low inductance. critical high - frequency components, such as rboot , cboot , rc snubber, and bypass capacitors, should be located as close to the respective ZSPM9015 module pins as possible on the top layer of the pcb. if this is not feasible, they can be connected from the backside through a network of low - inductance vias. figure 5 . 1 pcb layout example top view bottom view 6 glossary term description ccm continuous conduction mode dcm discontinuous conduction mode dis b driver disable hs high side ls low side thwn# thermal warning flag zcd zero current detection il inductor current
ZSPM9015 datasheet ? 2016 integrated device technology, inc. 22 january 25, 2016 7 ordering information product sales code description package ZSPM9015zi1r ZSPM9015 rohs - compliant qfn40 ? junction temperature range: 0c to 150c reel zspm8015 - kit evaluation kit for ZSPM9015 kit 8 related documents document zspm8015 - kit evaluation kit description visit idt ?s website www. idt .com or contact your nearest sales office for the latest version of these documents. 9 document revision history revision date description 1.00 april 26, 2013 first release 1. 10 a ugust 5 , 2013 minor updates to 1.1. maximum absolute rating : vswh added ; boot - pgnd values corrected. january 25, 2016 changed to idt branding. corporate headquarters 6024 silver creek valley road san jose, ca 95138 www.idt.com sales 1- 800- 345- 7015 or 408 - 284- 8200 fax: 408 - 284- 2775 www.idt.com/go/sales tech support www.idt.com/go/support disclaimer integrated device technology, inc. (idt) reserves the right to modify the products and/or specifications described herein at any time, without notice, at idt's sole discretion. performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer pro ducts. the information contained herein is provided without representation or warranty of any kind, whether express or implied, in cluding, but not limited to, the suitability of idt's products for any particular purpose, an implied warranty of merchantability, or non - infringement of the intellectual property rights of others. this document is presented only as a guide and does not co nvey any license under intellectual property rights of idt or any third parties. idt's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunct ion of an idt product can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are trademarks or registered trademarks of idt and its subsidiaries in the united states and other countries . other trademarks used herein are the property of idt or their respective third party owners. for datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary . all contents of this document are copyright of integrated device technology, inc. all rights reserved.

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